1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, a method of forming an alignment mark used in a photolithography process, which is one of the processes of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2006-215632, filed Aug. 8, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
Semiconductor devices such as a DRAM (dynamic random access memory) are manufactured by repeatedly performing a process of forming a wiring layer, a process of forming contact plugs for connecting upper and lower wiring lines, and the like, so as to form a plurality of wiring layers. For example, in order to reliably connect the upper and lower wiring lines via contact plugs, alignment (positioning) is necessary for preventing an offset between the connection position between lower-layer wiring and a contact plug therefor, and the connection position between corresponding upper-layer wiring and a contact plug therefor. Generally, in order to perform such alignment, alignment marks are formed on both (i) a reticle (i.e., a mask for exposure) on which circuit patterns are formed, and (ii) a semiconductor substrate. Alignment marks on the reticle are formed in advance when the reticle is fabricated. In contrast, alignment marks on the semiconductor substrate are formed in accordance with the progress of relevant processes, for example, in the vicinity of a scribe line, outside the element forming area.
Recently, detection of each alignment mark on the semiconductor substrate has been made difficult, due to (i) often performing a surface planarization process using a CMP (chemical mechanical polishing) technique, accompanied with fine structures of semiconductor devices, (ii) often using metal wiring materials which have no transparency, (iii) thin-filming with respect to a layer on which alignment marks are formed, or the like.
More specifically, in the alignment process, each alignment mark is optically read using an exposure apparatus such as a stepper. In this process, a step should be provided between the alignment mark and the periphery thereof, and the alignment mark should have a well-shaped form to a certain degree. If such conditions are not satisfied, the optical reading accuracy may be degraded, and reading itself may not be executed.
Patent Document 1 discloses a method of reliably detecting alignment marks. Patent Document 1 discloses an example of alignment marks, which have substantially the same structure as the gate of a MOS transistor, and which is used when performing alignment of a bit-line layer with respect to the gate. In this structure, a hollow part (called a “mark hole” in Patent Document 1) is formed in an inter-layer insulating film on a semiconductor substrate, so as to expose a surface of the substrate, and an alignment mark having the same structure as the gate is formed on the bottom face of the hollow part (i.e., on the surface of the semiconductor substrate). In accordance with this structure, even when a CMP process is applied on the upper surface of the inter-layer insulating film, the alignment mark, positioned on the bottom face of the hollow part, is not affected by the CMP process, thereby reliably detecting the alignment mark having a required step around it.
Patent Document 1: Japanese Unexamined Patent Application, First Publication No. 2001-36036.
However, generally, a plurality of alignment marks are arranged, each of which may have a rectangular pattern and a size of a few to dozens of micrometers. Therefore, when the technique disclosed in Patent Document 1 is applied to such alignment marks, the hollow part, formed by opening a part of the inter-layer insulating film, may have a length dimension greater than 100 μm in plan view. In this case of having a wide opening, even when alignment marks are positioned on the bottom face of the hollow part, it may be affected by the CMP process, and uneven polishing called “dishing” may occur, so that the step around each mark may be lowered, or the form of each mark may be deformed. In addition, even when the size of the opening is not so large, if the thickness of the inter-layer insulating film decreases in accordance with further fining of the semiconductor device, alignment marks may still be affected by the CMP process.
On the other hand, the alignment marks disclosed in Patent Document 1 have a considerable height, by which they tend to be affected by the CMP process. If the marks are made thinner so as to increase the distance between the upper surface of the inter-layer insulating film and the upper surface of the alignment mark, the alignment mark may be less affected by the CMP process. However, as described above, when the step of each alignment mark is lowered, detection of the alignment mark itself is difficult. That is, conventional techniques cannot simultaneously satisfy both (i) removal of affection of the CMP process on alignment marks, and (ii) reliable detection of alignment marks.